HBM4, the new fuel for AI engines | List of hardware components | GPU hardware | Hardware definition and examples | Turtles AI

SK Hynix has completed development and begun production readiness for HBM4, an ultra-high-bandwidth memory that doubles I/O and exceeds the JEDEC standard by 25%, while Micron and Samsung are hot on their heels.

Key Points:

• SK Hynix’s HBM4 is ready for industrial production.
• 2,048-bit interface and speeds over 10 Gbps per pin (+25% compared to JEDEC).
• 40% increased energy efficiency thanks to manufacturing innovations.
• Samsung and Micron are developing HBM4 stacks, but are lagging behind SK Hynix.

A new chapter in the universe of ultra-high-bandwidth memory is taking shape thanks to SK Hynix’s announcement: the South Korean company has officially completed internal certification of its 12-level HBM4 and has established a production chain capable of launching initial volumes in 2025. This milestone has pushed SK shares up more than 7%, well above the overall KOSPI performance.

The new generation doubles the number of I/O terminals from 1,024 to 2,048 and thus the bandwidth, bringing it to over 10 Gbps per pin, an increase of approximately 25% compared to the limit set by JEDEC. At the same time, the adoption of the proprietary MR-MUF process combined with 1bnm node DRAM technology enables 40% greater energy efficiency compared to the previous generation HBM3E.

Nvidia’s upcoming Rubin series AI GPUs—already previewed at GTC with specifications of 288 GB of HBM4 memory and up to 13 TB/s of aggregate bandwidth—and AMD, which aims to integrate up to 432 GB of HBM on MI400 series GPUs for the Helios project with nearly 20 TB/s, also rely on this advanced memory. This technical leap makes the product crucial for powering data center-level AI systems in 2026.

But the competition isn’t sitting idly by: Micron has begun shipping the first samples of 36 GB of HBM4 stacked with 12 layers and a 2,048-bit interface to customers, promising performance approximately double that of HBM3E. Samsung has also sent samples to potential customers and, according to recent sources, has passed qualification tests for Nvidia’s designs, starting pre-production by August 2025. However, its path has been marked by delays related to the yield of wafers in production, estimated at around 65% in July, with full volume expected only in 2026.

SK Hynix’s advantage, however, goes beyond speed: its HBM4s integrate a customer-specific logic die that makes it difficult to replace with competing offerings, strengthening its position as a preferred supplier, especially for Nvidia, which has already entrusted SK with the majority of its HBM offerings in recent years. Analysts expect SK Hynix to maintain a market share of over 60% by 2026, thanks in part to this first-mover advantage.

In parallel with the HBM4 race, SK has partnered with Sandisk to promote a hybrid memory standard called High Bandwidth Flash (HBF), which combines NAND flash and HBM-like architectures, offering capacities up to 8-16 times higher than DRAM and potential energy efficiency for edge-oriented AI workloads, although this technology will only debut by 2027.

The HBM4 landscape therefore presents a tension between SK Hynix’s consolidated leadership, technology pursuers such as Micron and Samsung, bold specifications of up to 16 layers, 64 GB per stack, and up to 2 TB/s of bandwidth per stack according to the 2025 JEDEC report, and global demand that is pushing AI giants to secure large-scale supplies in anticipation of the launch of new GPUs.

The promise of HBM4 thus provides a glimpse of the beating heart of the cutting-edge AI training infrastructure, and while SK Hynix prepares for mass production, Samsung and Micron are sharpening their weapons, each with different strategies and timescales.